Conventionally, facsimiles and digital copying machines have been known as data processing systems each of which is constituted by a CPU, a memory, I/O devices and a DMA controller. FIG. 9 is a block diagram showing the construction of a digital copying machine.
The digital copying machine in FIG. 9 is constituted by a scanner section having a CCD (Charge Coupled Device) 201 and an analog-signal processing section 202, a digital multi-value image processing section 203, a multi-value/binary conversion section 204, a binary/multi-value conversion section 205, a CPU 206, a memory 207, and a printer section having a laser control section 208 and a laser scan unit 209.
In the above-mentioned construction, an original document is irradiated by a light source (not shown) , and the reflected light is converted into an electric signal by the CCD 201. The weak electric signal is amplified, compensated for, and converted into a digital signal, that is, image data, by the analog-signal processing section 202. The image data is subjected to an image process such as an edge-emphasizing process by the digital multi-value image processing section 203 so as to enhance the image quality. In the multi-value/binary conversion section 204, the multi-value image is converted into a binary image by using a method such as an error dispersion method that is one of the methods for representing half tone with binary digits, in order to decrease the amount of data. The binary coded data is temporarily stored in the memory 207. Further, the binary coded data, read from the memory 207, is multi-value coded by the binary/multi-value conversion section 205. The laser control section 208 carries out a gradation process on the laser by means of a pulse-width modulation based upon the image data. The laser scan unit 209, which has a polygon motor (not shown) and a semiconductor laser (not shown) , projects a laser beam onto a charged photoconductor (not shown) so that a latent image is formed on the photoconductor. The CPU 206, in its CPU section, carries out various processes, such as setting registers in the various I/O devices, carrying out editing processes of the image data stored in the memory, such as a shading process for providing shadows diagonally to the lower right of characters, or overlaying distribution data of character data onto the image data.
In the above-mentioned digital copying machine, high-speed operations are required with respect to transfer operations, such as the transfer of the image data released from the multi-value/binary conversion section 204 to the memory 207 or the transfer of the image date stored in the memory 27 to the binary/multi-value conversion section 205. Accordingly, these transfers are often carried out directly without using the CPU 206. Moreover, in the case when processes, such as a rotation process for rotating an image by 90 degrees, are carried out on the image data, the internal transfer of the image data from the memory 207 to the memory 207 is often carried out directly without using the CPU 206. A DMA controller 210 controls such data transfers.
The conventional DMA controller 210 used in a digital copying machine has a construction shown in FIG. 10. In FIG. 10, the DMA controller 210 is provided with input terminals 221 and 223 for data-transfer request signals that respectively correspond to channels CH0 and CH1 and output terminals 222 and 224 for data-transfer response signals that respectively correspond to the channels CH0 and CH1. The transferred data is inputted and outputted in synchronism with the data-transfer response signals.
Here, in FIG. 10, the channel CH0 is connected to the output section of the multi-value/binary conversion section 204, that is an output-image buffer, which functions as an I/O device. The channel CH1 is connected to the input section of the binary/multi-value conversion section 205 that functions as an I/O device, that is, to an input-image buffer. Further, a channel CH2 and a channel CH3 are connected to a DRAM controller 211. The DRAM controller 211 is alternatively installed either in the CPU 206 or in the DMA controller 210, or placed independently; therefore, it is not shown in FIG. 9.
The DMA controller 210 is further provided with selectors 227 and 228 and counters 229 through 236.
The selector 227, upon receipt of a plurality of data-transfer request signals at the same time, makes a selection as to which data-transfer request signal should be taken first based upon a predetermined order of preference. Further, the selector 227, upon receipt of a data-transfer request signal with a higher order of preference during a transfer operation of data with a lower order of preference, carries out a reconciliation so as to transfer data in accordance with the order of preference.
The counters 229 through 232, which are installed for the corresponding channels CH0 through CH3, are counters used for creating addresses for the memory 207. These counters, 229 through 232, add and subtract addresses each time data is transferred. The addresses created in the counters 229 through 232 are selected by the selector 228, and sent to the DRAM controller 211.
The DRAM controller 211 converts the given addresses into a column address and a row address, and releases them to the memory 207 together with various control signals (*RAS, *CAS, etc.).
The counters 233 through 236, which are installed for the corresponding channels CH0 through CH3, are counters used for calculating the number of words of transferred data.
As described above, the conventional DMA controller 210 requires two counters for each channel, that is, the counter used for addresses and the counter used for calculating the number of words of transferred data. For this reason, the more the number of channels, the larger the circuit size becomes, resulting in high costs. This problem is particularly aggravated in apparatuses which have a large circuit size with a number of I/O devices.
In order to solve this problem, Japanese Laid-Open Patent Publication 250306/1991 (Tokukaihei 5-250306) discloses a DMA controller. In this DMA controller, registers are provided in place of the counters provided in the above-mentioned DMA controller 210, and a computing element, which is commonly used in all the channels, is provided so that addition of addresses and calculation of the number of words of transferred data are carried out by the computing element. Since registers require fewer gates than counters, this arrangement makes it possible to reduce the circuit size. Therefore, the application of such a DMA controller to a facsimile in the above-mentioned Laid-Open Patent Publication seems to reduce costs.
However, in the DMA controller disclosed in the above-mentioned Laid-Open Patent Publication, no consideration is given to a construction wherein the data transfer is carried out between the memories as well as between the memory and the I/O devices by using circuits with a small size, that is, a construction wherein multiple channels are achieved by using circuits with a small size.
Moreover, in recent years, multi-function apparatuses, which are composite apparatuses including facsimiles, digital copying machines, printers, etc., have been developed. In such multi-function apparatuses, high resolution has been achieved and the amount of data to be processed has been increased. Therefore, the multi-function apparatus tends to reduce the amount of memory so as to cut costs by eliminating a memory corresponding to one page that has been provided for each mode so that the memory can be commonly used.
In this case, a great many channels are required and when, upon receipt of a request for data transfer, the data cannot be transferred, lack of image might occur. Therefore, it is necessary for the multi-function apparatus to have a reconciling process that can deal with complex data-transfer requests.
However, in the DMA controllers of the above-mentioned Laid-Open Patent Publications, in the case when a plurality of requests for data transfer are made at the same time, even though it is possible to carry out a simple reconciling process for data-transfer requests, such as a data transfer based upon the predetermined order of preference, it is difficult to carry out a reconciling process for further complex data-transfer requests.
Moreover, even though a register requires fewer gates as compared with a counter, the difference is comparatively small. Therefore, the addition of a conciliation circuit for the reconciling process for complex data-transfer requests might rather increase the size of circuit.
Furthermore, although the DMA controllers of the above-mentioned Laid-Open Patent Publications are suitable for providing an optimal circuit for each specific system, it is difficult for them to maximize their hardware. In other words, since the computing element is commonly used in the respective channels, it is not possible to achieve maximization only by simply increasing the number of DMA macros.
In particular, it is not possible to carry out a memory-to-memory DMA process or to carry out a DMA process from a memory to an I/O device inside the same arrangement. Another problem is that since the transfer speed of image data has to be increased as the resolution increases, when the CPU changes the settings of the registers in accordance with a change in mode, the overhead time tends to increase in order to satisfy the settings.
Moreover, in the conventional DMA controllers, in the case when a data-transfer request is made from an I/O device during a memory-to-memory data transfer, the data-transfer of the I/O device is carried out after completion of the memory-to-memory data transfer; therefore, it is difficult to carry out another process by using the same arrangement. This is because very complicated software is required since the memory-to-memory data transfer and the data transfer from the I/O device to the memory are asynchronously operated.
Moreover, since the RISC (Reduced Instruction Set Computer) processor in the CPU carries out high-speed operations by pipeline-processing simple instructions at high speeds, the cycle time of the execution of instructions is faster than the access time of memories. For this reason, the RISC processor has a data cache and an instruction cache, and data and instructions from the external memory are loaded in the caches. Caches refer to special memories which are installed inside a CPU and to which the CPU makes a high-speed access. The CPU executes data and instructions inside the cache; however, the data and instructions to be executed are occasionally not available in the cache. This is referred to as a "miss-hit". In such a case, data and instructions located around addresses of a memory in which the necessary data and instructions have been stored are loaded to the cache. This operation is referred to as "refill". Since the necessary data and instructions are likely to exist at adjacent addresses, the greater the size of refill, the smaller the probability of miss-hit, resulting in a better performance of the CPU.
However, in the case when a data-transfer request is made during a refilling process, the operation can not be shifted until the refilling process has been completed. The data transfer is requested by the binary/multi-value conversion section 205 so as to print out data. In this case, loss of data might occur in a page printer such as a laser printer, unless the data is continuously sent thereto. This situation needs to be avoided by all means.
In systems using the conventional DMA controllers, in order to avoid loss of data even in the case when the shift is made after completion of the refilling process, the size of a data buffer in the I/O device such as a multi-value/binary conversion section 204 is increased, or the size of refill is decreased. In this case, the increased size of the data buffer causes the size of circuit to become bulky, and the decreased size of refill causes low performance of the CPU.